The invention generally relates to implantable cardiac stimulation devices and in particular to a hardware and software architecture for use therein.
A wide range of implantable cardiac stimulation devices are provided for surgical implantation into humans. One common example is the cardiac pacemaker. Another is the implantable cardioverter defibrillator (ICD). Current state of the art implantable devices typically include a general purpose programmable microprocessor for controlling the functions of the device such as detecting medical conditions within the patient in which the device is implanted and administering appropriate therapy. Within a pacemaker, for example, the microprocessor monitors the detection of P-waves and R-waves to determine whether an episode of bradycardia has occurred and, if so, administers a pacing pulse to the heart. Within an ICD, for example, the microprocessor analyzes P-waves, R-waves and other electrical signals of the heart to determine if an episode of ventricular fibrillation has occurred and, if so, administers a defibrillation shock to the heart.
In addition to performing functions directed to administering immediate therapy, the microprocessor coordinates all other functions of the implantable device such as: monitoring the power source of the device to determine if the power source needs to be replaced; switching of the mode of operation of the device from, for example, a single-chambered pacing mode to a dual-chambered pacing mode; and recording events for diagnostic purposes such as P-waves and R-waves, mode switching events and the administration of therapy. As implantable cardiac stimulation devices become more and more sophisticated, the number and complexity of functions that must be performed by the microprocessor increases as well. As a result, it becomes more and more difficult for the microprocessor to perform routine pacing functions while also performing the many higher level functions. To ensure that routine pacing functions are performed in a timely manner, faster and more powerful microprocessors are employed, resulting in greater power consumption in the device.
Accordingly, it would be desirable to provide an improved hardware architecture for use within an implantable cardiac stimulation device which eliminates the need for the microprocessor to perform routine pacing functions, thereby permitting the microprocessor to devote its resources primarily to performing higher level functions and it is to that end that aspects of the present invention are directed.
Also, when using a powerful general purpose microprocessor within an implantable cardiac stimulation device, it becomes increasingly difficult to develop software for controlling the microprocessor in a reliable and expedient manner. In this regard, a powerful microprocessor typically operates using a large and complex instruction set. Accordingly, software developed for controlling the microprocessor may need to be equally complex, resulting in a greater amount of time devoted to developing the software and still further time required for debugging the software. Also, with a microprocessor exploiting a complex instruction set, the risk of software bugs or other errors arising in the software becomes more significant. Accordingly, it would also be desirable to provide an improved software architecture for use within an implantable cardiac stimulation device, which expedites the prompt development of reliable software for use with implantable devices and it is to that end that other aspects of the invention are directed.
Insofar as both hardware and software development for implantable cardiac stimulation devices is concerned, it would be desirable to provide an improved technique for developing both the hardware and the software so as to ensure that the hardware and the software are optimized for use with one another to perform the required functions of the device, such as pacing functions, defibrillation functions, etc. In particular, it is desirable to provide an improved technique for developing hardware and software that minimizes development costs and also minimizes power consumption within the resulting device. Other aspects of the invention are directed to these ends.
In accordance with one aspect of the invention, an implantable cardiac stimulation device is provided for delivering therapy to heart tissue. The stimulation device includes a sensing circuit for sensing a cardiac signal from the heart tissue and an electrical therapy delivery circuit for delivering therapy to the heart tissue. A controller is provided which includes a programmable sequencer for analyzing the cardiac signal to determine whether therapy is needed and for controlling the electrical therapy delivery circuit to deliver therapy. The controller also includes a separate general purpose programmable microprocessor for performing non-therapy-delivering operations.
In an exemplary embodiment, wherein the implantable cardiac stimulation device is a pacemaker, the programmable sequencer controls routine pacing operations such as detection of P-waves and R-waves and the delivery of anti-bradycardia pacing pulses in response thereto. The programmable sequencer employs only a limited instruction set having twenty-two non-arithmetic instructions optimized for controlling routine pacing operations. In contrast, the programmable microprocessor is a complex instruction set computing (CISC) microprocessor or a conventional reduced instruction set computing (RISC) using a full instruction set. The programmable microprocessor is programmed to control all other operations of the pacemaker, such as lead impedance monitoring, battery monitoring and the storage of internal electrocardiogram (IEGM) signals and pacing events for subsequent transmission to an external programming device for analysis.
By providing a programmable sequencer for controlling routine pacing operations or other xe2x80x9clow-levelxe2x80x9d functions, the microprocessor is thereby free to devote its resources to performing all other xe2x80x9chigh-levelxe2x80x9d functions. Hence, the microprocessor may be operated at a lower clock frequency or duty cycle than would otherwise be needed if the microprocessor were also required to perform routine pacing functions, thereby saving power. By controlling all routine pacing operations with a programmable sequencer or state machine, the pacing operations are thereby more expediently performed. Moreover, because software for the sequencer is developed using only the first instruction set, routine pacing software is more expediently developed. Other higher level functions of the microprocessor are programmed using a more complex instruction set for performing a wider range of functions. Additional benefits are gained by isolating routine pacing software from the higher level functional software to permit, for example, the software of the microprocessor to be replaced without affecting the software of the sequencer, or vice versa. Both the microprocessor and sequencer may be reprogrammed after the device has been implanted within a patient by transmitting updated software into the device from an external programmer device.
In one specific example, the sequencer is an event-driven programmable state machine programmed to transition through a sequence of states based upon a sequence of instructions selected from the first instruction set. In another specific example, the sequencer is implemented as a RAM-based state machine.
In accordance with another aspect of the invention, a system and method is provided for developing a sequencer for use in an implantable cardiac stimulation device. In accordance with the method, a high-level software program is developed setting forth the functions to be performed by the sequencer using a high-level software design language. The high-level software program is then compiled to determine a minimum set of instructions needed to implement the functions. An automated hardware optimization tool processes the instructions to determine an optimal high-level hardware design for implementing the instructions. The high-level hardware configuration is output in a high-level hardware design language. The high-level hardware design is then processed using an automated hardware design tool to determine an optimal gate configuration. Thereafter, an integrated circuit (IC) sequencer is fabricated incorporating the optimal gate configuration.
In this manner, an IC is developed having the optimal transistor configuration to perform the operations required by the previously developed software. Thus, in contrast with many conventional techniques which merely optimize an IC configuration based upon a high-level hardware design, the method of the invention first optimizes the high-level hardware design based upon the software design, then optimizes the IC design based upon the optimized hardware design. Depending upon the particular implementation, the IC design may be optimized to, for example, minimize the number of transistor devices, circuit space, power consumption, or signal transmission routing delays. In this manner, once software has been designed to perform desired functions, a hardware device having the optimal IC configuration is easily developed based upon the software.
Additional advantages and features of the various aspects of the invention will be apparent from the descriptions below in combination with the accompanying drawings. Method and apparatus embodiments of the various aspects of the invention are provided.